Integrated circuit memory systems require some form of externally supplied voltage to carry out various memory operations, including memory read, program and erase operations. Typically, voltages of various magnitudes are required to carry out these operations. Memory systems generally utilize a primary power source having significant current capabilities. The primary power source is typically provided to the memory by an external source such as a power supply or battery. The primary power source, frequently referred to as V.sub.CC, is connected to the memory system by way of metal circuit pads formed on the integrated circuit itself. The primary supply voltage V.sub.cc typically has been set to +5 volts, although there has been a trend to reduce the voltage to +3.3 volts and even lower.
Memory systems also typically utilize voltages other than the primary supply voltage V.sub.CC for carrying out memory operations. By way of example, memory program operations for flash memory systems typically require application of a relatively large positive voltage to a selected one of the word lines of the flash cell array in order to carry out a programming operation. Such voltage, typically on the order of +12 volts, is sometimes referred to as voltage V.sub.PP. At the same time, a voltage V.sub.PPBL of intermediate value, typically on the order of +7 volts, is applied to a selected one of the bit lines of the flash cell array as part of the programming operation. In most applications, the bit line program voltage is derived from voltage V.sub.PP using an on-chip voltage regulator.
A typical conventional memory system may have a separate metal circuit pad for receiving the programming voltage V.sub.PP from an external source along with the pad for receiving voltage V.sub.CC. In the event single power supply operation is desired, a charge pump circuit can be implemented on the chip so that the externally supplied voltage V.sub.CC can be stepped up to voltage V.sub.PP.
As an example of a memory system utilizing a programming voltage V.sub.PP from an external source, the function of a conventional non-volatile flash memory system is shown in the block diagram of FIG. 1. The core of memory system 1 is an array 12 of memory cells. The individual cells in array 12 (not shown) are arranged in rows and columns, with there being, in this example, a total of 256 K eight bit words in array 12. Data input and output for the memory system 1 is accomplished by using an eight bit data bus DQ0-DQ7. The individual memory cells are accessed by using an eighteen bit address A0-A17, which is input by means of address pins 13. Nine of the eighteen address bits are used by X decoder 14 to select a word line associated with the row of array 12 in which a desired memory cell is located and the remaining nine bits are used by Y decoder 16 to select a bit line associated with the appropriate column of array 12 in which the desired cell is located. Sense amplifiers 50 are used to read the data contained in a memory cell during a read operation or during a data verification step in which the state of a cell is determined after a write or erase operation. The sense amplifier circuitry and verify circuits compare the state of the cell to a reference state corresponding to a programmed cell or an erased cell, depending upon the operation.
Writing or erasing of the memory cells in array 12 is carried out by applying the appropriate voltages to the source (source line), drain (bit line), and control gate (word line) of a cell for an appropriate time period. This causes electrons to tunnel or be injected from a channel region to a floating gate. The amount of charge residing on the floating gate determines the voltage required on the control gate in order to cause the device to conduct current between the source and drain regions. This is termed the threshold voltage of the cell with there being an erased threshold voltage V.sub.THE that is different from a programmed threshold voltage V.sub.THP. Conduction represents an "on" or erased state of the device and corresponds to a logic value of one. An "off" or programmed state is one in which current is not conducted between the source and drain regions and corresponds to a logic value of zero. By setting the threshold voltage of the cell to an appropriate value, the cell can be made to either conduct or not conduct current for a given set of applied voltages. Thus, by determining whether a cell conducts current at a given set of applied voltages, the state of the cell (programmed or erased) can be found.
Memory system 1 contains an internal state machine (ISM) 20 which controls the data processing operations and sub-operations performed on the memory cells contained in memory array 12. These include the steps necessary for carrying out writing, reading and erasing operations on the memory cells of array 12. In addition, internal state machine 20 controls operations such as reading or clearing status register 26, identifying memory system 1 in response to an identification command, and suspending an erase operation. State machine 20 functions to reduce the overhead required of an external processor (not depicted) typically used in association with memory system 1.
To avoid inadvertent programming of the memory device, programming commands (write or erase) consist of two cycles. The first cycle is a setup command wherein the code corresponding to the programming operation is written to the memory chip. To perform the setup command, the external processor causes the output enable pin OE to be inactive (high), and the chip enable CE and write enable WE pins to be active (low). The processor then places the 8 bit setup command code on data I/O pins 15 (DQ0-DQ7) and causes the chip enable CE and write enable WE pins to go inactive.
The command code for the first cycle of a write operation (write setup) is, for example, either 40 H (1000 0000) or 10 H (0001 0000). In the second cycle of a write sequence, after the chip enable CE and write enable WE pins are made inactive (high), the data to be written is placed on the data I/O pins 15 and the address of the memory location to be programmed is placed on the address pins 13 (A0-A17). The chip enable CE and write enable WE are again made active (low) while the programming voltage V.sub.PP is applied to a selected one of the word lines of memory device 1 by way of the X decoder 14. In addition, V.sub.PPBL is applied to the selected bit lines by Y decoder 16. The rising edge of the chip enable CE and write enable WE, whichever is later in time, causes the physical write operation on the memory cell to be initiated by application of the programming voltages to the cell.
Similarly, for an erase operation, the first cycle involves sending an erase setup command code such as 20 H (0010 0000) to the memory device 1. The second cycle of an erase, however, involves an erase confirm command code such as DOH (1101 0000) that is written to the memory device and the rising edge of chip enable CE and write enable WE initiates the erase cycle which erases either the entire memory array 12 or a block of memory locations within the array depending upon the functionality designed into the device.
The commands placed on data I/O pins 15 are transferred to data input buffer 22 and then to command execution logic unit 24. Command execution logic unit 24 receives and interprets the commands used to instruct state machine 20 to initiate and control the steps required for writing to array 12 or carrying out another desired operation. When a write operation is being executed, the data to be programmed into the memory cells is then input using data I/O pins 15, transferred to input buffer 22, and then placed in input data latch 30. The input data in latch 30 is then made available for the cell programming and data verification operations.
In the cell programming operation, an internal program pulse counter (not depicted) is initialized. This counter will keep track of the number of programming pulses that have been applied to the cells of the word (byte) being programmed. Next, a programming pulse is applied to the cells of the word located at the address placed on the address pins 13. The pulse counter is then incremented and a determination is made as to whether a predetermined maximum number of pulses have been applied to the cells. The cells are then checked, during a verify cycle, to determine whether they have, in fact, been programmed. If the cells are programmed, then the operation has executed successfully. If the cells are not programmed and the maximum number of pulses has not yet been reached, then another programming pulse is applied to the cells. Checking the programming state of the cells is accomplished using the sense amplifiers and associated components 50.
If the cells are still not programmed when the maximum pulse count is reached, then a failure has occurred because the maximum number of programming pulses have been applied to the cells. Depending upon the design of the particular memory, the sequence will be terminated or a record of the failed word will be made and the sequence continued. This information will then be transferred to the Status Register 26 so that it can be read by the processor. Once the desired write or erase operation sequence is completed, state machine 20 updates 8 bit status register 26. The content of the status register 26, in a typical memory device, indicates whether a successful write or erase sequence has been completed. The contents of status register 26 is transferred to data output buffer 28, which makes the contents available on data I/O pins 15 of memory system 1.
Typically, the programming voltage levels described above are permitted to vary by 10% from the specified level and the memory device will still operate correctly. However, if the voltage level falls outside the specified ranges, then the programming function may fail and corrupt the data stored in the memory cells or a successful programming operation would require an unacceptably long period of time. Also, the out-of-specification voltage levels are an indication of failure in the system to which the memory device is connected.
Conventional memory systems are typically only able to detect whether V.sub.PP drops below a preset voltage level such as +10 V during the programming operation. If V.sub.PP drops below the predetermined limit, then a voltage sense circuit will sense that an invalid voltage condition exists. At the beginning of a programming operation, or at any point at which the ISM 20 receives an indication that V.sub.PP is below the predetermined limit, the ISM 20 will abort the operation and set one or more status bits in the status register 26.
One common status bit in the status register 26 is a programming voltage error flag which indicates whether V.sub.PP was outside the specified limit during the operation. If V.sub.PP was outside the specified range, then the memory device may have aborted the operation, even if V.sub.PP dipped out of range only momentarily. If, during the verify cycle after a programming pulse has been applied, the ISM 20 detects that the programming voltage was out of the specified range, then it will halt the programming operation and set the programming voltage error flag. However, the programming state of the cells will already have been altered to some degree by the programming pulse.
Once a programming or erase operation has been completed, a user can access the status register 26 to determine the status of various parameters during the operation, including the status of V.sub.PP. If an erase operation was unsuccessful, the cause of the problem, such as low voltage levels, must be eliminated and the procedure repeated. However, if a write operation has been unsuccessful, it is very possible that the data in the memory system has been corrupted and recovery may not be possible. In some non-volatile memory systems, an unsuccessful write attempt may require that at least a portion of the memory array must be erased before another write operation may be performed at the same location in the array.
In addition, V.sub.PP voltage levels also typically sag as a result of the current drawn by the memory system to perform the programming operation. As a result, the voltage level of V.sub.PP may be above the predetermined limit prior to the initiation of the programming operation, but then drop below the limit as a consequence of the programming operation itself.
A memory system having the capability of monitoring the programming voltages and preventing programming operations from being initiated that are likely to be unsuccessful or to avoid aborting memory operations that have been initiated and will likely complete successfully would be very desirable. The present invention provides this and other capabilities as will become apparent to those skilled in the art upon a reading of the following Detailed Description of Specific Embodiments together with the drawings.